Insofar as applicants are aware, no method or apparatus has heretofore described how to implement division in finite field arithmetic in a bit-serial manner.
A paper entitled "Bit-Serial Reed-Solomon Encoders" published in the IEEE Trans. on Information Theory in Vol. IT-28, dated November 1982 at pp. 869-874, discloses a method for multiplying. This method requires representation of one of the multiplicands in a so-called dual basis.
In his PhD thesis entitled "Bit-Serial Reed-Solomon Decoders in VLSI" submitted to California Institute of Technology in 1984, D. L. Whiting described a method for converting from canonical to dual basis for a GF(2.sup.8) implementation.
Other prior art of background interest includes
"The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm" IEEE Trans. on Computers, Vol. C-33, October 1984, pp. 906-911.
"VLSI Architecture for Computing Multiplications and Inverses in GF(2.sup.m)", IEEE Trans. on Computers, Vol. C-34 August 1985, pp. 709-717.
"On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays", IEEE Trans. on Computers, Vol. 37 October 1988, pp. 1273-1280.
There is a need for a method and apparatus for effecting bit-serial division in a hardware cost-efficient manner.